This invention relates to standard cell digital logic chips; and more particularly, it relates to an improvement to such chips which enables minor logic changes to be made in a much quicker and less expensive fashion than has heretofore been possible.
Conventionally, a standard cell digital logic chip contains one to fifteen thousand standard logic cells which are arranged in rows on a semiconductor substrate. Cell interconnect channels of various widths lie between the rows. All of the standard logic cells that are on the chip are chosen by a chip designer from a library of at least 100 different types of cells, and each cell type in the library performs a different logic function. For example, one type of standard logic cell performs a five-input NAND function; another type of standard logic cell performs a three-input OR function, etc. Standard cells of a type that are commonly referred to as super-cells or megacells can also be in the library, and they include read/write memory arrays, read-only memory arrays, multiplier cells, and input/output buffers.
Each type of standard cell is made up of a respective number of transistors, and the number of transistors that are in a particular cell is the minimum number which is needed to perform the cell's logic function. This minimizing of the number of transistors per cell reduces the amount of chip space which the cell occupies, and thereby increases the total number of cells that can be put on a single chip. Also in each type of standard logic cell, the placement, the size, and the interconnections of the transistors are customized in order to further reduce the chip space which the cell occupies.
All of the transistors within a cell, as well as their placement and interconnection, are formed by several patterned conductive and insulative layers which are integrated together in a stack. Thus, to reduce the size of a cell as explained above, the shape of each of these layers must be customized. Consequently, each layer of every cell in the cell library has a unique and irregularly shaped pattern.
Such reduction in the size of the standard cells is a very important consideration because it enables a multi-chip product to be built with fewer chips, and that in turn enables the price of the product to be proportionately reduced. However, the present inventors have discovered that even when the size of every cell in the cell library is the smallest that is commercially available, the chips that are made from those cells still have a major deficiency. This deficiency relates to the speed at which logic errors on a chip can be fixed, and this deficiency can be so serious that it can actually determine the success or failure in the marketplace of a product which is made from the standard cell logic chips.
Accordingly, a primary object of the invention is to provide an improved standard cell logic chip in which the above deficiency, which is described fully in the Detailed Description, is corrected.